Table 1.  Consumer Electronics is Driving Large Memory Usage (Source:  iSuppli, Micron Technology, Denali Software)



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RAM vs NV Memories
SRAMs and DRAMs, whose fast read-write capabilities are necessary in most electronic systems, can be big power consumers in both the active and standby modes.  Leakage currents kill talk time.  Although the R-W performance and other functional limitations of silicon non-volatile memories…NOR and NAND Flash, or even EEPROMs…cannot compare to RAMs, systems designers are judicious in deciding how much RAM and how much NVM they need, and every effort is made to substitute NV for RAM wherever possible.  Memory growth in successive generations is now almost exclusively in the NOR or NAND flash, while the RAM portions remains rather static

NAND flash memory storage and DRAM capacity increases and shipment increase will drive to total storage capacity of semiconductor memory.

Standalone memories; embedded memories
In the natural evolution of chip complexes, chipsets and systems, higher levels of chip integration have been a great means of improving system performance, reducing power and reducing system size.  This is nothing new today, but we’ve seen that in some applications, the ‘transistor budget’ so exceeds system functional demand, that formerly standalone memories are being draw onto the main logic chip (MPU, APU, GPU), thereby reducing power requirements to drive signals off chip through packages and leads, and across board traces.  Integration is making everything more wonderful.

Figure 2.  Flash Memory NAND and DRAM Shipped Storage Capacity is Soaring.
 

Power down!! 
Power has been a check-off item for chips since the very beginning of the industry.  There has always been a small niche for which low power was imperative (calculators and watches, for example).  But, for the mainstream market, plugged into the wall outlet, it was always a secondary design priority.  Not so any more.  You either design for low power from the start, or face performance degradation problems at high clocks rates down the road.  Performance trends and demands, along with basic device physics, have pushed system performance up against a wall.  For laptops and cell phones, standby memory power is a significant part of the power drain and delimiter of battery life and operating (talk) time.

Furthermore, elements of the ‘low-power’ memory roadmap…features that were specifically developed and used to power reduce…are finding they way into the mainstream, standard power part.

Portability-driven space constrained packaging
The cell phone is the most remarkable piece of silicon technology available, and, with the right ‘calling service plan’, can be had by the consumer and user, virtually for free.  But despite its often-low consumer cost, it harbors both an immense amount of current technology today, and is pushing the frontier in many technology directions at once, for the future.

One group of these changes is the made necessary by the need to ‘fit it all into an enclosure that is 30-70 cubic cm.’.  For the memory stack, which includes SRAM or DRAM, NOR flash and/or NAND flash, and in some cases a removable flash card or HDD, space constraints have caused the rapid evolution of high density packages, multichip packages, and changes in the production process that allow the manufacturer to ensure the quality and reliability of the devices without first packaging each chip individually before it is tested and ‘burned in’.  Most bare die offered by the industry today go into cell phones, and they suffer no apparent deficiencies in quality, reliability, performance when compared with the traditionally packaged chips.

Of course, with higher packing densities and chips sitting on top of each other, power issues are multiplied, so that this compression of technology requires a commensurate effort to reduce power drain by each chip.

Drive cost out
The consumer segment is famous for its high volumes of production and the low prices it demands of its suppliers.  This is as true in the consumer silicon area as anywhere else, and the high volumes drive both chip vendor interest in the business, and also open up an avenue to cost reduction through its natural scale economies.  Where many companies are competing for same volume business, if you do not find a way to cost reduce your product, someone else likely will…especially if the prize is a consumer silicon market of 10M, 100M or 1B units…not unheard of in the consumer space.

With regard to each of these technology and prices trends individually, and all of them combined, “10 in 10” is not an excessive expectation…a ten-fold improvement in price performance within ten years, is by no means an unreasonable expectation… and far less that the distance that the PC, that stalwart, long-in-the-tooth market-driver of the ‘80s and ‘90s, has itself come in the past decade.

We have much to look forward to in the Silicon Home, and from what we have seen so far, the limits of technology are undiminished from decades ago, though the industry is more expensive to play in and more mature in its structure.